Some interrupt virtualization hardware provides support for avoiding some but not all guest intercepts during the lifetime of an interrupt. In particular, peripheral component interconnect express (PCIe) or other devices that send standard message signaled interrupt (MSI) or MSI-X interrupts involve a trip through a hypervisor before they can be delivered to a guest virtual central processing unit (VCPU). Handling interrupts in the hypervisor requires either dedicating a hypervisor core for handling interrupts or tolerating intercepts on some VCPU when the interrupt arrives.